In many present microprocessor systems, memory controllers are used to connect memory devices, such as DRAM (dynamic random access memory) devices to memory clients. Present memory controller systems often utilize a matrix of switches, such as a crossbar switch matrix, to interconnect a number N of memory devices to a number M of memory clients. FIG. 1 illustrates a presently known memory control system in which memory devices 102 are connected to memory clients 106 through a memory controller 104. In this typical memory controller system, any client 106 can access any memory device 102. This requires each memory device 102 to have a connection path (usually several traces) to each memory client 106. The memory controller 104 receives data request signals from the memory clients and in response, returns data to the clients after performing data access cycles over bi-directional lines connecting the memory controller to the memory devices.
The memory controller 104 typically includes a number of switches that route the request and return signal traces from each memory device to each client device. For layout purposes and to keep the trace lengths as short as possible between the memory devices and memory clients, the memory controller 104 is usually a unified circuit that is physically placed in the center of the integrated circuit (chip). For memory circuits that feature high densities, that is one with many memory devices and/or many memory clients, the number of request and return paths increases geometrically. This can result in very high wiring densities in the switching portion of the memory controller circuit, typically in the center of the chip. The high wiring density required by the memory controller switches can also result in high electrical noise during periods of increased memory access cycles.
Thus, present memory controller circuits, such as those illustrated in FIG. 1 are disadvantageous in that their layout requires that a memory controller be physically placed in the center of the chip, and contain a high wire density circuit, which can make layout and routing difficult, and create a high degree of noise and heat during operation.